With aggressive scaling of the FinFET technology design rule, use of a gate cut (CT) pillar for gate (PC) isolation becomes increasingly challenging. For example, in 7 nm technology, an incomplete CT is observed after the poly-open-chemical-mechanical-polishing (POC), thereby resulting in a PC to PC short. Though increasing the process time for a CT reactive-ion etching (RIE) may resolve this issue, it causes an increase in critical dimension (CD) of a CT. A large CD of CT reduces the process margin that may result in voids during work function (WF) metal fill.
A need, therefore, exists for devices with improved CT process margins with increased distance between the CT pillar and the fins in PC tip-to-tip, and for enabling methodology.